1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a fabrication method thereof.
2. Related Art
With miniaturization of digital apparatuses, high integration and miniaturization of semiconductor memory apparatuses are required. In particular, portable digital apparatuses have been increasingly distributed, and ultra-high integration, ultra-high speed, and ultra-low power of semiconductor memory apparatuses embedded in a limited size are required to process data in the limited size with higher speed.
To meet this demand, studies on vertical memory devices have been actively made.
FIG. 1 is a cross-sectional view illustrating a structure of a general vertical memory apparatus.
Referring to FIG. 1, a semiconductor substrate 101 in which a cell area C and a peripheral area P are defined by a device isolation layer 103 is provided.
A vertical memory device may be formed in the cell area C. For example, a cell switching device SW_C including a pillar 201 protruding perpendicular to a surface of the semiconductor substrate 101, and a gate insulating layer 203 and a gate conductive layer 205 surrounding a circumference of the pillar 201, are formed. A lower electrode 209 and a data storage unit 211 are formed to extend from an upper surface of the pillar 201 to a protrusion direction of the pillar 201. The data storage unit 211 may be formed using a material of which a resistance value is to be switched according to a voltage or a current supplied to the data storage unit 211. An upper electrode 213 is formed on an upper surface of the data storage unit 211. The upper electrode 213 may be coupled to a conductive line (not shown) through a metal contact 215. A metal silicide layer 207 may be additionally formed to improve between an interface resistance between the cell switching device SW_C and the lower electrode 209.
A core switching device SW_P may be formed in the peripheral area P.
The core switching device SW_P may have a structure in which a sidewall of each of a plurality of conductive stacks is surrounded by a gate insulating layer, and a hard mask 303 configured to protect the conductive stacks is formed on the core switching device SW_P. The core switching device SW_P may be coupled to an interconnection layer 307 through a junction contact 305, and the interconnection layer 307 may be coupled to each of conductive lines (not shown) through a metal contact 309.
The reference numerals 105, 107, and 109 denote interlayer insulating layers.
It may be seen from FIG. 1 that the vertical cell switching device SW_C formed in the cell area C may be formed by allowing the substrate to be recessed to a predetermined depth, forming the pillar 201, and forming a gate conductive layer 205 to surround the circumference of the pillar 201.
When the pillar 201 is formed in the cell area C, the peripheral area P is not recessed and an initial height of the peripheral area P is kept as it is. Thus, a height of an upper surface 101B of the semiconductor substrate 101 in the peripheral area P may be higher than a height of an upper surface 101A of the semiconductor substrate 101 in the cell area C.
When the semiconductor device is fabricated on the stepped semiconductor substrate, a height of the memory device formed in the cell area C is determined according to a height of the core switching device SW_P formed in the peripheral area P.
The core switching device SW_P is formed high in a multi-layered structure. The cell switching device SW_C is formed in the cell area C, and the core switching device SW_P is formed in the peripheral area P that is higher than the cell area C. Then, the interlayer insulating layer 107 is formed in the semiconductor substrate including the core switching device SW_P and a planarization process is performed on the interlayer insulating layer. However, since the core switching device SW_P is previously formed higher than an upper surface of the cell area C, it is difficult to precisely control the planarization process due to a large difference of height between the cell area C and the peripheral area P.
To form the lower electrode 209, a lower electrode contact hole is formed by patterning the interlayer insulating layer 107 formed in the cell area C. However, since a height of the interlayer insulating layer 107 depends on the height of the core switching device SW_P, an etching process of forming the lower electrode contact hole having a large aspect ratio is required. Further, since a process of gap-filling a lower electrode material in the lower electrode contact hole having the large aspect ratio is necessary, a level of difficulty in the process is increased and it is difficult to ensure yield.
Further, since a height of the lower electrode 209 formed in the cell area C depends on the height of the core switching device SW_P, there is a limitation in miniaturization of the semiconductor memory device.